I'm a bad DDR SDRAM controller

Timing	Value	Remarks
Speed (Mbps)		Not clock speed, transfer speed. Clock speed is half of this. Also called MT/s by Micron.
tRCDrd		RAS-to-CAS Delay (Read/Write) ACTIVATE-to-READ/WRITE command period An ACTIVATE command takes this many cycles to process. On Intel: tRCD controls both, set tRCDrd/tRCDwr to same.
tRCDwr
tCAS/tCL/tAA		CAS (Read) Latency A READ command takes this many cycles to process.
tCWL/tCWD		CAS (Write) Latency The RAM needs this many cycles to get ready to accept data after a WRITE command is issued.
tWR		Write Recovery Time Delay from an WRITE operation is started on RAM(after data is sent) to when a PRECHARGE command can be issued. It takes this many cycles for data to be moved into the core of RAM. On Intel: not configurable, calculated as tWR = tWRPRE(or tWRPDEN, see notes) - tCWL - BL/2
tRTP/tRDPRE		Read To Precharge Time READ-to-PRECHARGE command period It takes this many cycles for data to be moved back into the core of RAM. On DDR4 tWR = 2 * tRTP, always, as they share config register on the RAM.
tRP		Row Precharge Time PRECHARGE-to-ACTIVATE/REFRESH command period An PRECHARGE command takes this many cycles to process.
tRAS		Row Active Sustained Time ACTIVATE-to-PRECHARGE command period A row must stay active for at least this many cycles.
tRC		Row Cycling Time ACTIVATE-to-ACTIVATE/REFRESH command period The RAM needs this many cycles for its core to settle down after an ACTIVATE command. On Intel: not configurable, calculated as tRC = tRP + tRAS
tRRD_L(sg)		Row-to-Row Delay (Long, same group) ACTIVATE-to-ACTIVATE command period to different bank in same bank group. Wait this many cycles before activating another row in the same bank group.
tRRD_S(dg)		Row-to-Row Delay (Short, different group) ACTIVATE-to-ACTIVATE command period to different bank group. Wait this many cycles before activating another row in a different bank group.
tFAW		Four Activate Window Time At most 4 ACTIVATE commands can be sent to RAM in this many cycles.
tWTR_L(dg)		Write To Read Time (Long, same group) Delay from an WRITE operation is started on RAM(after data is sent) to issuing a READ command to a different bank in the same bank group. On Intel: not configurable, calculated as tWTR_L = tWrRd_sg - tCWL - BL/2 - 2 On AMD: check notes.
tWTR_S(dg)		Write To Read Time (Short, different group) Delay from an WRITE operation is started on RAM(after data is sent) to issuing a READ command to a different bank group. On Intel: not configurable, calculated as tWTR_S = tWrRd_dg - tCWL - BL/2 - 2 On AMD: check notes.
tRdRd_sg		Read-to-Read Delay same group READ-to-READ command period to different bank in same bank group. Wait this many cycles before reading from another bank in the same bank group. On AMD: Related to tRdRdScL, check notes.
tRdRd_dg		Read-to-Read Delay different group READ-to-READ command period to different bank group. Wait this many cycles before reading from another bank group. On AMD: Related to tRdRdSc, check notes.
tWrWr_sg		Write-to-Write Delay same group WRITE-to-WRITE command period to different bank in same bank group. Wait this many cycles before writing to another bank in the same bank group. On AMD: Related to tWrWrScL, check notes.
tWrWr_dg		Write-to-Write Delay different group WRITE-to-WRITE command period to different bank group. Wait this many cycles before writing to another bank group. On AMD: Related to tWrWrSc, check notes.
tRdWr_sg		Read-to-Write Delay same group READ-to-WRITE command period to different bank in same bank group. Wait this many cycles before reading from/writing to another bank in the same bank group. On AMD: check notes.
tRdWr_dg		Read-to-Write Delay different group READ-to-WRITE command period to different bank group. Wait this many cycles before reading from/writing to another bank group. On AMD: check notes.
tREFI		REFresh Interval Time Average cycles between REFRESH commands. In 2x mode this is cut in half, in 4x mode it's a quarter. And when the memory stick is running hot (like 85C hot) it also gets cut in half.
tRFC		ReFresh Cycle Time A REFRESH command takes this many cycles to process in normal (1x) refresh mode. Spec requires 8 REFRESH commands in 8x tREFI.
tRFC2	-	ReFresh Cycle Time (in 2x Refresh Mode) A REFRESH command takes this many cycles to process in 2x refresh mode. 2x and 4x mode refreshes fewer rows per command and needs to issue REFRESH more frequently. This one is probably called "2x refresh" or "Fine Granularity Refresh" in BIOS. Enabling this mode does not make RAM operable at higher temperatures. Extended temperature operation uses half tREFI with the normal tRFC, not tRFC2.
tRFC4	-	ReFresh Cycle Time (in 4x Refresh Mode) A REFRESH command takes this many cycles to process in 4x refresh mode. Might be unused, deleted in DDR5.
tCKE	-	ClocK Enable Time Minimum CKE signal pulse width CKE is used to put RAM into power save mode, if not using power save it's of no use.
I hate myself
tCR		Command Rate Hold Command/Address signals for this many cycles. C/A is latched into memory at the end of signaling.
BG Bits		Bank Group bits. Use 0 for DDR3, 1 for DDR4 x16, 2 for DDR4 x8/x4 and DDR5 x16, 3 for DDR5 x8/x4.
BA Bits		Bank Address bits. Usually 2 for DDR4/DDR5, 3 for DDR3, 1 on some low-capacity DDR5 memory.
CA Bits		Column Address bits. 11 for DDR5 x4, 10 for everything else.
BL (log2)		Burst Length. Use 3(BL=8) for DDR3/DDR4, 4(BL=16) for DDR5.
DDR5		Try to emulate DDR5 (2 cycle ACT/READ/WRITE). Command scheduling will be extra bad.
Gear-Down		Gear-Down Mode (DDR4) Latch Command/Address every other cycle only. tCL/tCWL/tWR/tRTP must be even when enabled.

Notes on AMD's t(Rd/Wr)(Rd/Wr)(Sc(L)) parameters:

I'm not entirely sure what tRdRdSc(L)/tWrWrSc(L)/tRdWr/tWrRd control or how they control RAM timings. My current theory is that tRdRdSc(L)/tWrWrSc(L) = tRdRd_dg(sg)/tWrWr_dg(sg) - 3 as otherwise these should not accept 1, 2 or 3 as valid settings(DQ/DQS bus would be busy carrying out another command at tCL/tCWL cycles after the commands are issued). AMD does not publish register/AGESA documentation so this is merely a guess.

Following that tRdWr most likely controls both tRdWr_sg and tRdWr_dg, and sets them to tRdWr + 3.

However this theory breaks for tWrRd, so what it does is not clear to me. If like previous timings this sets tWrRd_sg/dg then setting 1 makes no sense. Issuing READ while there is an WRITE in-flight is forbidden by spec and some RAM would lock up if you try that. Besides, on AMD tWTR is configurable. So um?

Some rambling on Intel's tWrRd and tWTR:

On Intel tWTR_S(L) = tWrRd_dg(sg) - tCWL - BL/2 - 2
I'm not convinced on the "-2" part being there just because, but I don't know enough to figure out why it's there.

Also on DDR5, BL=16 and some utilities written in the DDR4 era would still assume BL=8 and show the wrong value for tWTR_S/L on Intel DDR5 platforms(tWTR_S/L DOES NOT EXIST on Intel). And maybe, just maybe, if your UEFI BIOS allows setting tWTR_S/L on Intel DDR5 platform it could also be calculating tWRPRE with the wrong BL.

So when the new DDR5 AMD platform comes along(I'm writing this in Aug. 2022) and manages lower tWTR timing by exactly 4, it might not be that Intel's IMC is crap but because utilities are displaying tWTR wrong.

Some rambling on Intel's tWR:

TLDR: To set tWR on Intel, either set tWRPDEN = tWRPRE = tCWL + BL/2 + tWR, or set tWRPRE and disable power down.

tWRPDEN is Time between WRite command and Power Down ENable, as it implies this controls how soon can the RAM enter power down(pulling CKE low), not accept a PRECHARGE command, after it has accepted a WRITE command. If only tWRPDEN is set and not tWRPRE, this would only tune tWR when there's no more thing to do for the RAM and you have power down mode enabled. If power down is disabled setting tWRPDEN does nothing.

In case you're browsing memory datasheet or reading SPD data:

All the t(RdRd/WrWr/RdWr)_sg timings are lumped into one timing: tCCD_L. (CAS-to-CAS Delay Long)
All the t(RdRd/WrWr/RdWr)_dg timings are lumped into one timing: tCCD_S. (CAS-to-CAS Delay Short)
tCL becomes tAA.

Where are the _dr and _dg timings?

I do not want to add ranks/DIMMs, it's already complicated enough.

What are the RAS/CAS thing?

Commands are encoded onto the RAS/CAS/WE/AP signal lines(see cycle table). RAS/CAS refers to 2 of the lines.